Bejoy Thomas

library ieee; use ieee.std_logic_1164.all; entity bejoy_jkff is port(j,k,clk:in std_logic;q,q1,z:inout std_logic); end bejoy_jkff; architecture arc of bejoy_jkff is begin process(clk) begin if clk='1' then z q q1 end if; end process; end arc;

library ieee; use ieee.std_logic_1164.all; entity bejoy_tff is port(t,clk:in std_logic;q,q1,z:inout std_logic); end bejoy_tff; architecture arc of bejoy_tff is begin process(clk) begin if clk='1' then z q q1 end if; end process; end arc;

library ieee; use ieee.std_logic_1164.all; entity bejoy_rsff is port(s,r,clk:in std_logic;q,q1,z:inout std_logic); end bejoy_rsff; architecture arc of bejoy_rsff is begin process(clk) begin if clk='1' then z q q1 end if; end process; end arc;

library ieee; use ieee.std_logic_1164.all; entity bejoy_dff is port(d,clock :in std_logic; Q:out std_logic); end bejoy_dff; architecture arc of bejoy_dff is begin process(clock) begin if clock'event and clock='1' then Q end if; end process; end arc;

library ieee; use ieee.std_logic_1164.all; entity bejoy_3x8 is port(a,b,c:in std_logic; d0,d1,d2,d3,d4,d5,d6,d7:out std_logic); end bejoy_3x8; architecture arc of bejoy_3x8 is begin d0 d1 d2 d3 d4 d5 d6 d7 end arc;

library ieee; use ieee.std_logic_1164.all; entity bejoy_8x3 is port(d0,d1,d2,d3,d4,d5,d6,d7:in std_logic; a0,a1,a2:out std_logic); end bejoy_8x3; architecture arc of bejoy_8x3 is begin a2 a1 a0 end arc;

library IEEE; use IEEE.std_logic_1164.all; entity bejoy_1x4 is port(s1,s2,data_in : in std_logic; d1,d2,d3,d4 : out std_logic); end bejoy_1x4; architecture arc of bejoy_1x4 is component dmux port(sx1,sx2,d : in std_logic; z1,z2 : out std_logic); end component; begin dmux1 : dmux port map(s1,s2,data_in,d1,d2); dmux2 : dmux port map(not s1,s2,data_in,d3,d4); end arc; library ieee; use ieee.std_logic_1164.all; entity dmux is port(sx1,sx2,d :in std_logic; z1,z2: out std_logic); end dmux; architecture arc of dmux is begin z1 z2 end arc;