VHDL code for 1x4 Demultiplexer using structural style

library IEEE;
use IEEE.std_logic_1164.all;

entity bejoy_1x4 is
port(s1,s2,data_in : in std_logic;
d1,d2,d3,d4 : out std_logic);
end bejoy_1x4;

architecture arc of bejoy_1x4 is

component dmux
port(sx1,sx2,d : in std_logic;
z1,z2 : out std_logic);
end component;

begin
dmux1 : dmux port map(s1,s2,data_in,d1,d2);
dmux2 : dmux port map(not s1,s2,data_in,d3,d4);
end arc;

library ieee;
use ieee.std_logic_1164.all;

entity dmux is
port(sx1,sx2,d :in std_logic;
z1,z2: out std_logic);
end dmux;

architecture arc of dmux is
begin
z1 <= d and (not sx1) and (not sx2);
z2 <= d and (not sx1) and sx2;
end arc;

Comments

Master Slave JK Flip Flop

library ieee; use ieee.std_logic_1164.all; entity master_slave_jk is port(j,k,clk:in std_logic;q1,q1x,z1x:inout std_logic; q2,q2x,z2x: inout std_logic); end master_slave_jk; architecture arc of master_slave_jk is begin process(clk) begin if clk='1' then z1x<=(j and (not q2)) or ((not k)and q2); q1<=z1x after 5 ns; q1x<=not z1x after 5ns; else z2x<=(q1 and (not q2)) or ((not q1x)and q2); q2<=z2x after 5 ns; q2x<=not z2x after 5ns; end if; end process; end arc;

VHDL code for 1x2 Demultiplexer

library ieee; use ieee.std_logic_1164.all; entity bejoy_1x2 is port(d,s:in std_logic; z0,z1:out std_logic); end bejoy_1x2; architecture arc of bejoy_1x2 is begin z0 z1 end arc;

VHDL code for Even Parity Generator

library ieee; use ieee.std_logic_1164.all; entity bejoy_ep is port(x,y,z:in std_logic; p:out std_logic); end bejoy_ep; architecture a of bejoy_ep is begin p end a;

Bejoy Thomas

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