library ieee; use ieee.std_logic_1164.all; entity bejoy_op is port(x,y,z:in std_logic; p:out std_logic); end bejoy_op; architecture a of bejoy_op is begin p end a;
library ieee; use ieee.std_logic_1164.all; entity bejoy_ep is port(x,y,z:in std_logic; p:out std_logic); end bejoy_ep; architecture a of bejoy_ep is begin p end a;