library ieee;
use ieee.std_logic_1164.all;
entity bejoy_rsff is
port(s,r,clk:in std_logic;q,q1,z:inout std_logic);
end bejoy_rsff;
architecture arc of bejoy_rsff is
begin
process(clk)
begin
if clk='1' then
z<=s or ((not r) and q);
q<=z after 5ns;
q1<=not z after 5ns;
end if;
end process;
end arc;
use ieee.std_logic_1164.all;
entity bejoy_rsff is
port(s,r,clk:in std_logic;q,q1,z:inout std_logic);
end bejoy_rsff;
architecture arc of bejoy_rsff is
begin
process(clk)
begin
if clk='1' then
z<=s or ((not r) and q);
q<=z after 5ns;
q1<=not z after 5ns;
end if;
end process;
end arc;
Helped me a lot in lab!! Thank you :)
ReplyDeletevery nice but you should have written it in terms of edge trigger and not the level trigger.For detecting EDGE the construst is rising_edge(clk).
ReplyDeleteBTW nice work
Thank you so much!
ReplyDelete