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Master Slave JK Flip Flop




library ieee;
use ieee.std_logic_1164.all;

entity master_slave_jk is
port(j,k,clk:in std_logic;q1,q1x,z1x:inout std_logic;
q2,q2x,z2x: inout std_logic);
end master_slave_jk;

architecture arc of master_slave_jk is
begin
process(clk)
begin

if clk='1' then

z1x<=(j and (not q2)) or ((not k)and q2);
q1<=z1x after 5 ns;
q1x<=not z1x after 5ns;

else

z2x<=(q1 and (not q2)) or ((not q1x)and q2);
q2<=z2x after 5 ns;
q2x<=not z2x after 5ns;

end if;
end process;
end arc;
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Comments

  1. deepak taraFebruary 28, 2011 at 10:12 PM

    can u dig it

    ReplyDelete
  2. AnonymousOctober 9, 2011 at 11:28 AM

    sir it will become much easier to understand the code if you could show the intermediate signals such as z1x,q1x etc in the circuit diagram.

    ReplyDelete
  3. AnonymousMarch 6, 2012 at 1:21 AM

    give details as to what is z1, z2, q1, q2

    ReplyDelete
  4. AnonymousMarch 25, 2012 at 11:01 AM

    nice one

    ReplyDelete

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