library ieee;
use ieee.std_logic_1164.all;
entity bejoy_g2b is
port(g:in std_logic_vector(3 downto 0);
b:inout std_logic_vector(3 downto 0));
end bejoy_g2b;
architecture a of bejoy_g2b is
begin
b(3)<=g(3);
b(2)<=b(3) xor g(2);
b(1)<=b(2) xor g(1);
b(0)<=b(1) xor g(0);
end a;
use ieee.std_logic_1164.all;
entity bejoy_g2b is
port(g:in std_logic_vector(3 downto 0);
b:inout std_logic_vector(3 downto 0));
end bejoy_g2b;
architecture a of bejoy_g2b is
begin
b(3)<=g(3);
b(2)<=b(3) xor g(2);
b(1)<=b(2) xor g(1);
b(0)<=b(1) xor g(0);
end a;
thanks a lot brother
ReplyDeleteu have posted general programs & what i want to suggest u is create the combination of projects for designing a particular project.
ReplyDeleteeg: If we want to design a digital calculator, how can we approach to design it.
like that if u design ,it will be useful to u a lot & also to others like me....
please take it as +ve way.
Hey im also electr. And comm. Engg.will u help me somthing in study plz .im in b.tech 2nd yr.frm india
ReplyDeleteGood Work.
ReplyDeletethank you ;)
ReplyDeletecan u use FOR loop after b(3)<=g(3) statement??
can you give the test bench of the programe
ReplyDelete