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VHDL code for Basic Gates

AND Gate

library ieee;

use ieee.std_logic_1164.all;

entity and_gate is

port (a,b : in std_logic ;

c : out std_logic);

end and_gate;

architecture arc of and_gate is

begin

c <= a and b; end arc;


OR Gate


library ieee;

use ieee.std_logic_1164.all;

entity or_gate is

port (a,b : in std_logic ;

c : out std_logic);

end or_gate;

architecture arc of or_gate is

begin

c <= a or b; end arc;



NOT Gate


library ieee;

use ieee.std_logic_1164.all;

entity not_gate is

port (a: in std_logic ;

b : out std_logic);

end not_gate;

architecture arc of not_gate is

begin

b <= not a; end arc;


NAND Gate


library ieee;

use ieee.std_logic_1164.all;

entity nand_gate is

port (a,b : in std_logic ;

c : out std_logic);

end nand_gate;

architecture arc of nand_gate is

begin

c <= a or b; end arc;


NOR Gate


library ieee;

use ieee.std_logic_1164.all;

entity nor_gate is

port (a,b : in std_logic ;

c : out std_logic);

end nor_gate;

architecture arc of nor_gate is

begin

c <= a nor b; end arc;


XOR Gate


library ieee;

use ieee.std_logic_1164.all;

entity xor_gate is

port (a,b : in std_logic ;

c : out std_logic);

end xor_gate;

architecture arc of xor_gate is

begin

c <= a xor b;

end arc;

Comments

  1. thank you so much for this blog. it was very useful to me!! i am new to vhdl and so it helped me a lot!!!!

    ReplyDelete
  2. nice one............

    ReplyDelete
  3. Thanx a lot, these are really helpful.
    Do you have the codes for Multiplexer? 1 bit and 2bit?

    ReplyDelete
    Replies
    1. entity counter is
      Port ( clk,reset : in std_logic;
      q : out std_logic_vector(1 downto 0));
      end counter;

      architecture Behavioral of counter is
      type state is (st0,st1,st2,st3);
      signal pstate,nstate:state;
      begin
      process(clk,reset)
      begin
      if(reset='1')then
      pstate<=st0;
      elsif(clk='1' and clk'event)then
      pstate<=nstate;
      else
      null;
      end if;
      end process;
      process(pstate)
      begin
      case pstate is
      when st0=>
      q<="00";
      nstate<=st1;
      when st1=>
      q<="01";
      nstate<=st2;
      when st2=>
      q<="10";
      nstate<=st3;
      when st3=>
      q<="11";
      nstate<=st0;
      end case;
      end process;

      end Behavioral;

      Delete
    2. entity counter is
      Port ( clk,reset : in std_logic;
      q : out std_logic_vector(1 downto 0));
      end counter;

      architecture Behavioral of counter is
      type state is (st0,st1,st2,st3);
      signal pstate,nstate:state;
      begin
      process(clk,reset)
      begin
      if(reset='1')then
      pstate<=st0;
      elsif(clk='1' and clk'event)then
      pstate<=nstate;
      else
      null;
      end if;
      end process;
      process(pstate)
      begin
      case pstate is
      when st0=>
      q<="00";
      nstate<=st1;
      when st1=>
      q<="01";
      nstate<=st2;
      when st2=>
      q<="10";
      nstate<=st3;
      when st3=>
      q<="11";
      nstate<=st0;
      end case;
      end process;

      end Behavioral;

      Delete
    3. kindly send me the code for PID controller...i'll be highly thankfull to you for this fovor

      Delete
  4. u r awwsum dude

    ReplyDelete
  5. yeah it is good.. but please also mention architecture's type that it is solved in behaviour type or structural type or else..

    ReplyDelete
  6. need behavior codes pl...

    ReplyDelete
  7. thank you very much

    ReplyDelete

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VHDL code for 4x1 Multiplexer using structural style

library IEEE;
use IEEE.std_logic_1164.all;

entity bejoy_4x1 is
port(s1,s2,d00,d01,d10,d11 : in std_logic;
z_out : out std_logic);
end bejoy_4x1;

architecture arc of bejoy_4x1 is

component mux
port(sx1,sx2,d0,d1 : in std_logic;
z : out std_logic);
end component;

component or_2
port(a,b : in std_logic;
c : out std_logic);
end component;

signal intr1, intr2, intr3, intr4 : std_logic;
begin
mux1 : mux port map(s1,s2,d00,d01,intr1);
mux2 : mux port map(not s1,s2, d10,d11,intr2);
o1 : or_2 port map(intr1, intr2, z_out);
end arc;

library ieee;
use ieee.std_logic_1164.all;

entity mux is
port(sx1,sx2,d0,d1 :in std_logic;
z1,z2: inout std_logic;
z: out std_logic);
end mux;

architecture arc of mux is
begin
z1 <= d0 and (not sx1) and (not sx2);
z2 <= (d1 and (not sx1) and sx2);
z<= z1 or z2;
end arc;

entity or_2 is
port(a,b : in bit;
c : out bit);
end or_2;
architecture arc of or_2 is
begin
c<=a or b;
end arc;

VHDL code for Full Adder using structural style

library IEEE;
use IEEE.std_logic_1164.all;

entity bejoy_fa is
port(In1,In2,c_in : in std_logic;
sum, c_out : out std_logic);
end bejoy_fa;

architecture arc of bejoy_fa is

component half_adder
port(a,b : in std_logic;
sum, carry : out std_logic);
end component;

component or_2
port(a,b : in std_logic;
c : out std_logic);
end component;

signal s1, s2, s3 : std_logic;

begin

H1: half_adder port map(a=>In1, b=>In2, sum=>s1, carry=>s3);

H2: half_adder port map(a=>s1, b=>c_in, sum=>sum, carry=>s2);

O1: or_2 port map(a=> s2, b=>s3, c=>c_out);

end arc;

entity half_adder is

port (a,b : in bit ;
sum,carry : out bit);

end half_adder;

architecture arc of half_adder is

begin

sum<= a xor b;
carry <= a and b;

end arc;

entity or_2 is

port (a,b : in bit ;
c : out bit);

end or_2;

architecture arc of or_2 is

begin

c<= a or b;

end arc;