VHDL code for 4 bit Gray to Binary converter

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_g2b is
port(g:in std_logic_vector(3 downto 0);

b:inout std_logic_vector(3 downto 0));
end bejoy_g2b;


architecture a of bejoy_g2b is
begin

b(3)<=g(3);
b(2)<=b(3) xor g(2);
b(1)<=b(2) xor g(1);
b(0)<=b(1) xor g(0);
end a;