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VHDL code for 1x4 Demultiplexer using structural style

library IEEE;
use IEEE.std_logic_1164.all;

entity bejoy_1x4 is
port(s1,s2,data_in : in std_logic;
d1,d2,d3,d4 : out std_logic);
end bejoy_1x4;

architecture arc of bejoy_1x4 is

component dmux
port(sx1,sx2,d : in std_logic;
z1,z2 : out std_logic);
end component;

begin
dmux1 : dmux port map(s1,s2,data_in,d1,d2);
dmux2 : dmux port map(not s1,s2,data_in,d3,d4);
end arc;

library ieee;
use ieee.std_logic_1164.all;

entity dmux is
port(sx1,sx2,d :in std_logic;
z1,z2: out std_logic);
end dmux;

architecture arc of dmux is
begin
z1 <= d and (not sx1) and (not sx2);
z2 <= d and (not sx1) and sx2;
end arc;

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