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VHDL code for T Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_tff is
port(t,clk:in std_logic;q,q1,z:inout std_logic);
end bejoy_tff;

architecture arc of bejoy_tff is
begin
process(clk)
begin

if clk='1' then
z<=((t and (not q)) or ((not t) and q));
q<=z after 5ns;
q1<=not z after 5ns;

end if;
end process;
end arc;

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VHDL code for 4x1 Multiplexer using structural style

library IEEE;
use IEEE.std_logic_1164.all;

entity bejoy_4x1 is
port(s1,s2,d00,d01,d10,d11 : in std_logic;
z_out : out std_logic);
end bejoy_4x1;

architecture arc of bejoy_4x1 is

component mux
port(sx1,sx2,d0,d1 : in std_logic;
z : out std_logic);
end component;

component or_2
port(a,b : in std_logic;
c : out std_logic);
end component;

signal intr1, intr2, intr3, intr4 : std_logic;
begin
mux1 : mux port map(s1,s2,d00,d01,intr1);
mux2 : mux port map(not s1,s2, d10,d11,intr2);
o1 : or_2 port map(intr1, intr2, z_out);
end arc;

library ieee;
use ieee.std_logic_1164.all;

entity mux is
port(sx1,sx2,d0,d1 :in std_logic;
z1,z2: inout std_logic;
z: out std_logic);
end mux;

architecture arc of mux is
begin
z1 <= d0 and (not sx1) and (not sx2);
z2 <= (d1 and (not sx1) and sx2);
z<= z1 or z2;
end arc;

entity or_2 is
port(a,b : in bit;
c : out bit);
end or_2;
architecture arc of or_2 is
begin
c<=a or b;
end arc;

VHDL code for Basic Gates

AND Gate

library ieee;

use ieee.std_logic_1164.all;

entity and_gate is

port (a,b : in std_logic ;

c : out std_logic);

end and_gate;

architecture arc of and_gate is

begin

c <= a and b; end arc;


OR Gate

library ieee;

use ieee.std_logic_1164.all;

entity or_gate is

port (a,b : in std_logic ;

c : out std_logic);

end or_gate;

architecture arc of or_gate is

begin

c <= a or b; end arc;



NOT Gate

library ieee;

use ieee.std_logic_1164.all;

entity not_gate is

port (a: in std_logic ;

b : out std_logic);

end not_gate;

architecture arc of not_gate is

begin

b <= not a; end arc;


NAND Gate

library ieee;

use ieee.std_logic_1164.all;

entity nand_gate is

port (a,b : in std_logic ;

c : out std_logic);

end nand_gate;

architecture arc of nand_gate is

begin

c <= a or b; end arc;


NOR Gate

library ieee;

use ieee.std_logic_1164.all;

entity nor_gate is

port (a,b : in std_logic ;

c : out std_logic);

end nor_gate;

architecture arc of nor_gate is

begin

c <= a nor b; end arc;


XOR Gate

library ieee;

use ieee.std_logic_1164.all;

ent…

VHDL code for Full Adder using structural style

library IEEE;
use IEEE.std_logic_1164.all;

entity bejoy_fa is
port(In1,In2,c_in : in std_logic;
sum, c_out : out std_logic);
end bejoy_fa;

architecture arc of bejoy_fa is

component half_adder
port(a,b : in std_logic;
sum, carry : out std_logic);
end component;

component or_2
port(a,b : in std_logic;
c : out std_logic);
end component;

signal s1, s2, s3 : std_logic;

begin

H1: half_adder port map(a=>In1, b=>In2, sum=>s1, carry=>s3);

H2: half_adder port map(a=>s1, b=>c_in, sum=>sum, carry=>s2);

O1: or_2 port map(a=> s2, b=>s3, c=>c_out);

end arc;

entity half_adder is

port (a,b : in bit ;
sum,carry : out bit);

end half_adder;

architecture arc of half_adder is

begin

sum<= a xor b;
carry <= a and b;

end arc;

entity or_2 is

port (a,b : in bit ;
c : out bit);

end or_2;

architecture arc of or_2 is

begin

c<= a or b;

end arc;