Wednesday, December 23, 2009

VHDL code for JK Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_jkff is
port(j,k,clk:in std_logic;q,q1,z:inout std_logic);
end bejoy_jkff;

architecture arc of bejoy_jkff is
begin
process(clk)
begin

if clk='1' then
z<=(j and (not q)) or ((not k) and q);
q<=z after 5ns;
q1<=not z after 5ns;

end if;
end process;
end arc;

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