Wednesday, December 23, 2009

VHDL code for Half Adder

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_ha is

port (a,b : in bit ;

s,c : out bit);

end bejoy_ha;

architecture arc of bejoy_ha is

begin

s<= a xor b;
c <= a and b;

end arc;

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