VHDL code for D Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_dff is
port(d,clock :in std_logic;
Q:out std_logic);
end bejoy_dff;

architecture arc of bejoy_dff is

begin
process(clock)
begin

if clock'event and clock='1' then
Q<=D;

end if;
end process;
end arc;