library ieee;
use ieee.std_logic_1164.all;
entity bejoy_8x3 is
port(d0,d1,d2,d3,d4,d5,d6,d7:in std_logic;
a0,a1,a2:out std_logic);
end bejoy_8x3;
architecture arc of bejoy_8x3 is
begin
a2<= d4 or d5 or d6 or d7;
a1<= d2 or d3 or d6 or d7;
a0<= d1 or d3 or d5 or d7;
end arc;
use ieee.std_logic_1164.all;
entity bejoy_8x3 is
port(d0,d1,d2,d3,d4,d5,d6,d7:in std_logic;
a0,a1,a2:out std_logic);
end bejoy_8x3;
architecture arc of bejoy_8x3 is
begin
a2<= d4 or d5 or d6 or d7;
a1<= d2 or d3 or d6 or d7;
a0<= d1 or d3 or d5 or d7;
end arc;
How do you simplified it became this?
ReplyDeletefrom the truth table select the corresponding 1s in the given column. check out Anand Kumar for details.
ReplyDeleteplease write the code for encoder 4:2 please
ReplyDeletewats the difference in program if its a priority encoder
ReplyDelete