Wednesday, December 23, 2009

VHDL code for 8x3 Encoder

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_8x3 is
port(d0,d1,d2,d3,d4,d5,d6,d7:in std_logic;

a0,a1,a2:out std_logic);
end bejoy_8x3;

architecture arc of bejoy_8x3 is
begin
a2<= d4 or d5 or d6 or d7;
a1<= d2 or d3 or d6 or d7;
a0<= d1 or d3 or d5 or d7;
end arc;

4 comments:

  1. How do you simplified it became this?

    ReplyDelete
  2. from the truth table select the corresponding 1s in the given column. check out Anand Kumar for details.

    ReplyDelete
  3. please write the code for encoder 4:2 please

    ReplyDelete
  4. wats the difference in program if its a priority encoder

    ReplyDelete