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VHDL code for 3x8 Decoder

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_3x8 is
port(a,b,c:in std_logic;
d0,d1,d2,d3,d4,d5,d6,d7:out std_logic);
end bejoy_3x8;

architecture arc of bejoy_3x8 is
begin
d0<= (not a) and (not b) and (not c);
d1<= (not a) and (not b) and c;
d2<= (not a) and b and (not c);
d3<= (not a) and b and c;
d4<= a and (not b) and (not c);
d5<= a and (not b) and c;
d6<= a and b and (not c);
d7<= a and b and c;
end arc;

Comments

  1. Thank you!!!! This is great help for me who is just starting to learn VHDL. BTW, is it possible to replace each output port (d0, d1 etc.) to std_logic_vector (7 downto 0)? I mean, reducing the hassle of typing every out port?

    ReplyDelete

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use ieee.std_logic_1164.all;

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library ieee;

use ieee.std_logic_1164.all;

entity nand_gate is

port (a,b : in std_logic ;

c : out std_logic);

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library ieee;

use ieee.std_logic_1164.all;

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port (a,b : in std_logic ;

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library ieee;

use ieee.std_logic_1164.all;

ent…

VHDL code for 4x1 Multiplexer using structural style

library IEEE;
use IEEE.std_logic_1164.all;

entity bejoy_4x1 is
port(s1,s2,d00,d01,d10,d11 : in std_logic;
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port(a,b : in std_logic;
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signal intr1, intr2, intr3, intr4 : std_logic;
begin
mux1 : mux port map(s1,s2,d00,d01,intr1);
mux2 : mux port map(not s1,s2, d10,d11,intr2);
o1 : or_2 port map(intr1, intr2, z_out);
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use ieee.std_logic_1164.all;

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port(sx1,sx2,d0,d1 :in std_logic;
z1,z2: inout std_logic;
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port(a,b : in bit;
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VHDL code for Full Adder using structural style

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port(In1,In2,c_in : in std_logic;
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