Wednesday, December 23, 2009

VHDL code for 3x8 Decoder

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_3x8 is
port(a,b,c:in std_logic;
d0,d1,d2,d3,d4,d5,d6,d7:out std_logic);
end bejoy_3x8;

architecture arc of bejoy_3x8 is
d0<= (not a) and (not b) and (not c);
d1<= (not a) and (not b) and c;
d2<= (not a) and b and (not c);
d3<= (not a) and b and c;
d4<= a and (not b) and (not c);
d5<= a and (not b) and c;
d6<= a and b and (not c);
d7<= a and b and c;
end arc;

1 comment:

  1. Thank you!!!! This is great help for me who is just starting to learn VHDL. BTW, is it possible to replace each output port (d0, d1 etc.) to std_logic_vector (7 downto 0)? I mean, reducing the hassle of typing every out port?