VHDL code for 1x2 Demultiplexer

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_1x2 is
port(d,s:in std_logic;

z0,z1:out std_logic);
end bejoy_1x2;

architecture arc of bejoy_1x2 is
begin
z0 <= d and (not s);
z1 <= (d and s);
end arc;