VHDL code for Odd Parity Generator

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_op is
port(x,y,z:in std_logic;
p:out std_logic);
end bejoy_op;

architecture a of bejoy_op is
begin
p<=((x xor y) xor z);
end a;

VHDL code for Even Parity Generator

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_ep is
port(x,y,z:in std_logic;
p:out std_logic);
end bejoy_ep;

architecture a of bejoy_ep is
begin
p<=((x xor y) xnor z);
end a;