Master Slave JK Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity master_slave_jk is
port(j,k,clk:in std_logic;q1,q1x,z1x:inout std_logic;
q2,q2x,z2x: inout std_logic);
end master_slave_jk;

architecture arc of master_slave_jk is
begin
process(clk)
begin

if clk='1' then

z1x<=(j and (not q2)) or ((not k)and q2);
q1<=z1x after 5 ns;
q1x<=not z1x after 5ns;

else

z2x<=(q1 and (not q2)) or ((not q1x)and q2);
q2<=z2x after 5 ns;
q2x<=not z2x after 5ns;

end if;
end process;
end arc;

VHDL code for JK Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_jkff is
port(j,k,clk:in std_logic;q,q1,z:inout std_logic);
end bejoy_jkff;

architecture arc of bejoy_jkff is
begin
process(clk)
begin

if clk='1' then
z<=(j and (not q)) or ((not k) and q);
q<=z after 5ns;
q1<=not z after 5ns;

end if;
end process;
end arc;

VHDL code for T Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_tff is
port(t,clk:in std_logic;q,q1,z:inout std_logic);
end bejoy_tff;

architecture arc of bejoy_tff is
begin
process(clk)
begin

if clk='1' then
z<=((t and (not q)) or ((not t) and q));
q<=z after 5ns;
q1<=not z after 5ns;

end if;
end process;
end arc;

VHDL code for SR Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_rsff is
port(s,r,clk:in std_logic;q,q1,z:inout std_logic);
end bejoy_rsff;

architecture arc of bejoy_rsff is
begin
process(clk)
begin

if clk='1' then
z<=s or ((not r) and q);
q<=z after 5ns;
q1<=not z after 5ns;

end if;
end process;
end arc;

VHDL code for D Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_dff is
port(d,clock :in std_logic;
Q:out std_logic);
end bejoy_dff;

architecture arc of bejoy_dff is

begin
process(clock)
begin

if clock'event and clock='1' then
Q<=D;

end if;
end process;
end arc;