Friday, August 28, 2015

Pune..
















Sunday, July 26, 2015

Mandvi Kutch





Jaisalmer Windfarm

Jaisalmer Wind Farm

Saturday, April 18, 2015

Delhi & NCR Region

India Gate



Lodhi Garden







Hymayun's Toumb






Qutub Minar


Hauz Khaz Village

Tuesday, December 29, 2009

Master Slave JK Flip Flop




library ieee;
use ieee.std_logic_1164.all;

entity master_slave_jk is
port(j,k,clk:in std_logic;q1,q1x,z1x:inout std_logic;
q2,q2x,z2x: inout std_logic);
end master_slave_jk;

architecture arc of master_slave_jk is
begin
process(clk)
begin

if clk='1' then

z1x<=(j and (not q2)) or ((not k)and q2);
q1<=z1x after 5 ns;
q1x<=not z1x after 5ns;

else

z2x<=(q1 and (not q2)) or ((not q1x)and q2);
q2<=z2x after 5 ns;
q2x<=not z2x after 5ns;

end if;
end process;
end arc;

Wednesday, December 23, 2009

VHDL code for Odd Parity Generator

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_op is
port(x,y,z:in std_logic;
p:out std_logic);
end bejoy_op;

architecture a of bejoy_op is
begin
p<=((x xor y) xor z);
end a;

VHDL code for Even Parity Generator

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_ep is
port(x,y,z:in std_logic;
p:out std_logic);
end bejoy_ep;

architecture a of bejoy_ep is
begin
p<=((x xor y) xnor z);
end a;